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AD800

Features: Standard Products44.736 Mbps-DS-351.84 Mbps-STS-1155.52 Mbps-STS-3 or STM-1Accepts NRZ Data, No Preamble RequiredRecovered Clock and Retimed Data OutputsPhase-Locked Loop Type Clock Recovery-No Crystal RequiredRandom Jitter: 208 Peak-to-PeakPattern Jitter: Virtually Eliminated10KH ECL Co...

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SeekIC No. : 004271423 Detail

AD800: Features: Standard Products44.736 Mbps-DS-351.84 Mbps-STS-1155.52 Mbps-STS-3 or STM-1Accepts NRZ Data, No Preamble RequiredRecovered Clock and Retimed Data OutputsPhase-Locked Loop Type Clock Recove...

AD800 Data Sheet

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Part Number:
AD800
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Standard Products
44.736 Mbps-DS-3
51.84 Mbps-STS-1
155.52 Mbps-STS-3 or STM-1
Accepts NRZ Data, No Preamble Required
Recovered Clock and Retimed Data Outputs
Phase-Locked Loop Type Clock Recovery-No Crystal Required
Random Jitter: 208 Peak-to-Peak
Pattern Jitter: Virtually Eliminated
10KH ECL Compatible
Single Supply Operation: 5.2 V or +5 V
Wide Operating Temperature Range: 408C to +858C




Pinout

AD800 Diagram




Specifications

Data Rate (Gb/s) 156Mbps
Voltage Supply (V) -5.5V
Package 20-Lead SOIC
Jitter Tolerance (Ulpp) .9 UI @ 65 kHz
Input Sensitivity (mVp-p) 80mV p-p


Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage (Pin 16 or Pin 17 to VCC) . . . . VEE to +300 mV
Maximum Junction Temperature
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range . . . . . . . . . . .65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . .+300°C
ESD Rating
AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V




Description

The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products AD800 and AD802 described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and 52 Mbps STS-1 are supported by the AD800-45 and AD800-52 respectively. 155 Mbps STS-3 or STM-1 are supported by the AD802-155.

Unlike other PLL-based clock recovery circuits, these devices AD800 and AD802 do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data. The
phase-lock loop then acquires the phase of the input data, and ensures that the phase of the output signals track changes in the phase of the input data. The loop damping of the circuit is dependent on the value of a user selected capacitor; this defines jitter peaking performance and impacts acquisition time. The devices AD800 and AD802 exhibit 0.08 dB jitter peaking, and acquire lock on random or scrambled data within 4 × 105 bit periods when using a damping factor of 5.




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