ACTS630MS

Features: •Devices QML Qualified in Accordance with MIL-PRF-38535•Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96721 and Intersil's QM Plan•1.25 Micron Radiation Hardened SOS CMOS•Total Dose . . . . . . . . . . . . . . . . . . . . . . . . ...

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ACTS630MS Picture
SeekIC No. : 004268140 Detail

ACTS630MS: Features: •Devices QML Qualified in Accordance with MIL-PRF-38535•Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96721 and Intersil's QM Plan•1.25 ...

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Part Number:
ACTS630MS
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

•Devices QML Qualified in Accordance with MIL-PRF-38535
•Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96721 and Intersil's QM Plan
•1.25 Micron Radiation Hardened SOS CMOS
•Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300K RAD (Si)
•Single Event Upset (SEU) Immunity:<1 x 10 -10 Errors/Bit/Day (Typ)
•SEU LET Threshold. . . . . . . . . . . . . . . . . . . . . . .>100 MEV-cm 2/mg
•Dose Rate Upset . . . . . . . . . . . . . . . .>10 11 RAD (Si)/s, 20ns Pulse
•Dose Rate Survivability. . . . . . . . . . .>1012 RAD (Si)/s, 20ns Pulse
•Latch-Up Free Under Any Conditions
•Military Temperature Range . . . . . . . . . . . . . . . . . .-55oC to +125oC
•Significant Power Reduction Compared to ALSTTL Logic
•DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
•Input Logic Levels-VIL = 0.8V Max-VIH = VCC/2 Min
•Input Current1µA at VOL, VOH
•Fast Propagation Delay. . . . . . . . . . . . . . . .37ns (Max), 24ns (Typ)



Pinout

  Connection Diagram


Description

   The Intersil ACTS630MS is a Radiation Hardened 16-bitparallel errordetection and correction circuit. It uses amodified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken form memory and checked for errors. Single bit errors in the data words are flagged and corrected. Sin-gle bit errors in check words are flagged but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which isoutput during the error correction cycle.

   The ACTS630MS utilizes advanced CMOS/SOS technology to achieve  high-speed operation. This device is a member of a radiation hardened,high-speed, CMOS/SOS Logic Family.The ACTS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or a 28 Lead Ceramic Dual-In-Line Package (D suffix).

 


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