ACTS280MS

Features: • Devices QML Qualified in Accordance with MIL-PRF-38535• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96720 and Intersil' QM Plan• 1.25 Micron Radiation Hardened SOS CMOS• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . ....

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ACTS280MS Picture
SeekIC No. : 004268124 Detail

ACTS280MS: Features: • Devices QML Qualified in Accordance with MIL-PRF-38535• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96720 and Intersil' QM Plan• 1.25 Micr...

floor Price/Ceiling Price

Part Number:
ACTS280MS
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96720 and Intersil' QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
       - VIL = 0.8V Max
       - VIH = VCC/2 Min
• Input Current £ 1mA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 24ns (Max), 16ns (Typ)



Pinout

  Connection Diagram


Description

The Intersil ACTS280MS is a Radiation Hardened 9-bit odd/even parity generator checker device. Both odd and even parity outputs are available for generating or checking parity for words up to 9 bits long. Even parity is indicated (EVEN output high) when an even number of data inputs are high. Odd parity is indicated (ODD output high) when an odd number of data inputs are high. Parity checking for larger words can be accomplished by tying EVEN output to any input of an additional ACTS280MS.

The ACTS280MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family.

The ACTS280MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix).



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