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ACS373MS

Features: • 1.25 Micron Radiation Hardened SOS CMOS• Total Dose 300K RAD (Si)• Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ)• SEU LET Threshold >80 MEV-cm2/mg• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse• Latch-Up Free Under Any Con...

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SeekIC No. : 004267889 Detail

ACS373MS: Features: • 1.25 Micron Radiation Hardened SOS CMOS• Total Dose 300K RAD (Si)• Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ)• SEU LET Threshold >80 ...

ACS373MS Data Sheet

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Part Number:
ACS373MS
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity  <1 x 10-10 Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm2/mg
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55 to +125
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current 1A at VOL, VOH


Pinout

Connection Diagram


Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +6.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . -0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . ±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . .±50mA
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 to +150
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . +265
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
(All Voltages Reference to VSS)


Description

The Intersil ACS373MS is a radiation hardened octal transparent latch with three-state outputs. The outputs are transparent to the inputs when the latch enable (LE) is high. When the LE goes low,the data is latched. When the Output Enable (OE) is high, the outputs are in the high impedance state. The latch operation is independent of the state of the output enable.

The ACS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family.




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