9DB106BGLFT

Specifications

Temperature C Voltage 3.3 V Package TSSOP 28 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade Multiplication/Divide Value


Description

PCIE BUFFER
The ICS9DB106 zero-delay buffer supports PCI Express clockingrequirements. The ICS9DB106 is driven by a differential SRC outputpair from an ICS CK409/CK410-compliant main clock generatorsuch as the ICS952601 or ICS954101. It attenuates jitter on theinput clock and has a selectable PLL bandwidth to maximizeperformance in systems with or without Spread-Spectrum clocking.

ICS9DB106 Output Features:

6 - 0.7V current mode differential output pairs (HSCL)

SMBus for complete device control

28-pin SSOP, TSSOP