87C196LB

Features: 20 MHz operation† 24 Kbytes of on-chip OTPROM 768 bytes of on-chip register RAM Register-to-register architecture Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines Integrated, industry-standard J1850 communication protocol Six-channel/10-bit...

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SeekIC No. : 004257135 Detail

87C196LB: Features: 20 MHz operation† 24 Kbytes of on-chip OTPROM 768 bytes of on-chip register RAM Register-to-register architecture Peripheral transaction server (PTS) with high-speed, microcoded inte...

floor Price/Ceiling Price

Part Number:
87C196LB
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

 20 MHz operation†
24 Kbytes of on-chip OTPROM
768 bytes of on-chip register RAM
Register-to-register architecture
Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines
Integrated, industry-standard J1850 communication protocol
Six-channel/10-bit A/D with sample and hold
High-speed event processor array
    -Six capture/compare channels
    -Two compare-only channels
    -Two 16-bit software timers
Full-duplex serial I/O port with dedicated baud-rate generator
Enhanced full-duplex, synchronous serial I/O port (SSIO)
 Programmable 8- or 16-bit external bus
Optional clock doubler with programmable clock output signal
SFR register that indicates the source of the last reset
Design enhancements for EMI reduction
Oscillator failure detection circuitry
Watchdog timer (WDT)
40 to +125 ambient temperature
52-pin PLCC package



Pinout

  Connection Diagram


Specifications

Storage Temperature .................................... 60 to +150
Voltage from VPP or EA# to VSS or ANGND... 0.5V to +13.0 V
Voltage from any other pin to VSS or ANGND...0.5V to +7.0V
Power Dissipation .......................................................... 0.5 W



Description

The 87C196LB is a high-performance 16-bit microcontroller with integrated support for the J1850 communication protocol. The 87C196LB is composed of a high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock speed as a more costly 8 MHz resonator in previous applications. This same circuitry of 87C196LB can drive other devices where a separate resonator was required in the past. Another costsavings feature of 87C196LB is the fact that the I/O ports are driven low at reset, avoiding the need for pull-up resistors.


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