74VHCT125A

` HIGHSPEED: tPD = 3.8 ns (TYP.) atV<sub>CC</sub>= 5V
` LOWPOWERDISSIPATION:
    I_CC =4 mA (MAX.) at T_A =25 ^oC
` COMPATIBLEWITH TTL OUTPUTS:
    V<sub>IH</sub> =2V(MIN),V<sub>IL</sub> = 0.8V(MAX)
` POWERDOWN PROTECTIONON INPUTS& OUTPUTS
` SYMMETRICAL OUTPUT IMPEDANCE:
    |I<sub>OH</sub>| = I<sub>OL</sub> = 8 mA(MIN)
` BALANCEDPROPAGATIONDELAYS:
    t_PLH t_PHL
` OPERATINGVOLTAGERANGE:
    V<sub>CC</sub> (OPR)= 4.5Vto 5.5V
` PINANDFUNCTION COMPATIBLEWITH 74 SERIES125
` IMPROVEDLATCH-UP IMMUNITY
` LOWNOISE:V_OLP = 0.8V(Max.)

AbsoluteMaximumRatingsarethose values beyond whichdamage to the device may occur. Functional operation under these condition isnot implied.
1)Output in OFFState
2) High or Low State

The 74VHCT125A is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

This device requires the 3-STATE control input G to be set high to place the output into the high impedance state.

Power down protection of the 74VHCT125A is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs of the 74VHCT125A are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.