74VHC573

Features:

`HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V
`LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25°C
`HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.)
`POWER DOWN PROTECTION ON INPUTS
`SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)
`BALANCED PROPAGATION DELAYS: tPLH  tPHL
`OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V
`PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
`IMPROVED LATCH-UP IMMUNITY
`LOW NOISE: VOLP = 0.9V (MAX.)


Pinout




Specifications

SYMBOL	PARAMETER	Value	UNIT
VCC	Supply voltagee	0.5 to+ 7.0	V
VI	DC Input Voltage	0.5 to+ 7.0	V
VO	DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	- 20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Current	±25	mA
ICC or IGND	DC VCC or Ground Current	± 75	mA
Tstg	Storage temperature	65 to 150
TL	Lead Temperature (10 sec)	300

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied


Description

The 74VHC573 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C²MOS technology.

These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely.

When the LE is taken low, the Q outputs of the 74VHC573 will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage.

This 74VHC573 can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.