Features: `HIGHSPEED: tPD =5.5ns (TYP.) at VCC = 5V`LOWPOWERDISSIPATION: ICC =4 A (MAX.) at TA =25 `HIGHNOISEIMMUNITY: VNIH=VNIL =28%VCC (MIN.)`POWERDOWN PROTECTIONON INPUTS`SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA(MIN)`BALANCEDPROPAGATIONDELAYS: tPLH @ tPHL`OPERATINGVOLTAGERANGE: VCC (OPR...
74VHC238: Features: `HIGHSPEED: tPD =5.5ns (TYP.) at VCC = 5V`LOWPOWERDISSIPATION: ICC =4 A (MAX.) at TA =25 `HIGHNOISEIMMUNITY: VNIH=VNIL =28%VCC (MIN.)`POWERDOWN PROTECTIONON INPUTS`SYMMETRICAL OUTPUT IMPED...
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SYMBOL | PARAMETER | Value | UNIT |
VCC | Supply voltagee | 0.5 to+ 7.0 | V |
VI | DC Input Voltage | 0.5 to+ 7.0 | V |
VO | DC Output Voltage | -0.5 to VCC + 0.5 | V |
IIK | DC Input Diode Current | - 20 | mA |
IOK | DC Output Diode Current | ± 20 | mA |
IO | DC Output Current | ±25 | mA |
ICC or IGND | DC VCC or Ground Current | ± 70 | mA |
Tstg | Storage temperature | 65 to 150 | |
TL |
Lead Temperature (10 sec) | 300 |
The 74VHC238 is an advanced high-speed CMOS 3 TO 8 LINE DECODER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
If the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs will go high. If enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all the 8 outputsgo to low.
Three enable inputs are provided to ease cascade connection and application of this address decoders for memory systems.
Power down protection of the 74VHC238 is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.
All inputs and outputs of the 74VHC238 are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.