74LVXZ161284

The 74LVXZ161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side).

Outputs of the 74LVXZ161284 on the cable side can be configured to be either open drain or high drive (± 14 mA) and are connected to a separate power supply pin (V_CC-Cable) that allows these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, the C inputs and the B and Y outputs on the cable side contain internal pull-up resistors connected to the V_CC-Cable supply to provide proper input termination and pull-ups for open drain output mode.

Outputs of the 74LVXZ161284 on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A₁A₈/B₁B₈ transceiver pins.

This 74LVXZ161284 also has an added power-up protection feature which forces the Y outputs (Y₉ - Y₁₃) to a high state after power-on until one of the associated inputs (A₉ - A₁₃) goes HIGH. When an associated input (A₉ - A₁₃) goes HIGH, all
Y outputs (Y₉ - Y₁₃) are activated.