74LVX161284A

Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals with the exception of output slew rate
Translation capability allows outputs on the cable side to interface with 5V signals
All inputs have hysteresis to provide noise margin
B and Y output resistance optimized to drive external cable
B and Y outputs in high impedance mode during power down
Inputs and outputs on cable side have internal pull-up resistors
Flow-through pin configuration allows easy interface between the "Peripheral and Host"
Replaces the function of two (2) 74ACT1284 devices

The 74LVX161284A contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard, with the exception of output slew rate, and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side).

Outputs of the 74LVX161284A on the cable side can be configured to be either open drain or high drive (±14 mA) and are connected to a separate power supply pin (V_CCcable) to allow these outputs to be driven by a higher supply voltage than the Aside. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the V_CCcable supply to provide proper termination and pull-ups for open drain mode.

Outputs on the Peripheral side of the 74LVX161284A are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1A8/B1B8 transceiver pins.