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74LVT2952

Features: •8-bit registered transceiver•Independent registers for A and B buses•Output capability: +64mA/-32mA•TTL input and output switching levels•Input and output interface capability to systems at 5V supply•Bus-hold data inputs eliminate the need for externa...

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SeekIC No. : 004251526 Detail

74LVT2952: Features: •8-bit registered transceiver•Independent registers for A and B buses•Output capability: +64mA/-32mA•TTL input and output switching levels•Input and output in...

74LVT2952 Data Sheet

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Part Number:
74LVT2952
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/2/15

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Product Details

Description



Features:

•8-bit registered transceiver
•Independent registers for A and B buses
•Output capability: +64mA/-32mA
•TTL input and output switching levels
•Input and output interface capability to systems at 5V supply
•Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
•Live insertion/extraction permitted
•No bus current loading when output is tied to 5V bus
•Power-up reset
•Power-up 3-State
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +4.6 V
IIK DC input diode current V1 < 0 -50 mA
VI DC input voltage3   0.5 to +7.0 V
IOK DC output diode current VO < 0 -50 mA
VOUT DC output voltage3 Output in Off or High state 0.5 to +7.0 V
IOUT DC output current Output in High state -64 mA
Output in Low state 128
Tstg Storage temperature range   65 to 150 °C



Description

The 74LVT2952 is a high-performance BiCMOS product designed for VCC operation at 3.3V.

This device combines  low static and dynamic power dissipation with high speed and  high output drive.

The 74LVT2952 device is an 8-bit registered transceiver. Two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses.

Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (CEXX</a>) is Low.The data is then present at the 3-State output buffers, but is only accessible when the Output Enable (OEXX</a>) is Low. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.




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