74LVT16652A

Features:

• 16-bit bus interface
• 3-State buffers
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
• No bus current loading when output is tied to 5V bus
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		0.5 to +7.0	V
IIK	DC input diode current	VI < 0	18	mA
VI	DC input voltage3		1.2 to +7.0	V
IOK	DC output diode current	VO < 0	50	mA
VOUT	DC output voltage3	output in Off or High state	0.5 to +5.5	V
IOUT	DC output current	output in Low state	128	mA
		Output in High state	64
Tstg	Storage temperature range		65 to 150	°C

Description

The 74LVT16652A is a high-performance BiCMOS product designed for VCC operation at 3.3V. The device can be used as two 8-bit transceivers or one 16-bit transceiver.

Complimentary output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A Low-input level selects real-time data, and a High input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.

Data of the 74LVT16652A on the A or B bus, or both, can be stored in the internal flip-flops by Low-to-High transitions at the appropriate clock (CPAB or CPBA) inputs regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration.