Features: •16-bit universal bus interface
•3-State buffers
•Output capability: +64mA/-32mA
•TTL input and output switching levels
•Input and output interface capability to systems at 5V supply
•Bus-hold data inputs eliminate the need for external pull-up esistors to hold unused inputs
•Live insertion/extraction permitted
•Power-up 3-State
•Power-up reset
•No bus current loading when output is tied to 5V bus
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015 nd 200V per Machine Model
Pinout
Specifications
| SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
| VCC |
DCsupplyvoltage |
|
0.5 to +4.6 |
V |
| IIK |
DC input diode current |
VI0 |
50 |
mA |
| VI |
DC input voltage3 |
|
0.5 to +7.0 |
V |
| IOK |
DC output diode current |
VO0 |
-50 |
mA |
| VOUT |
DC output voltage3 |
outputinOfforHighstate |
0.5 to +7.0 |
V |
| IOUT |
DC output current |
output in Low state |
128 |
mA |
| Output in High state |
64 |
| Tstg |
Storage temperature range |
|
-65 to 150 |
|
DescriptionThe 74LVT16543A is a high-performance BiCMOS product esigned for VCC operation at 3.3V. The device can be used as two -bit transceivers or one 16-bit transceiver.
The 74LVT16543A contains two sets of eight D-type latches, with eparate control pins for each set. Using data flow from A to B as an xample, when the A-to-B Enable (nEAB) input and the A-to-B Latch nable (nLEAB) input are Low, the A-to-B path is transparent.
A subsequent Low-to-High transition of the nLEAB signal puts the A ata into the latches where it is stored and the B outputs no longer hange with the A inputs. With nEAB and nOEAB both Low, the -State B output buffers are active and display the data present at he outputs of the A latches.
Control of data flow from B to A is similar, but using the nEAB, LEBA , and nOEBA inputs.
Active bus-hold circuitry of the 74LVT16543A is provided to hold unused or floating data nputs at a valid logic level.
74LVT16543A Data Sheet
