74LVT16373A

Features: 16-bit transparent latch 3-State buffers Output capability: +64mA/-32mA TTL input and output switching levels Input and output interface capability to systems at 5V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live inser...

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SeekIC No. : 004251496 Detail

74LVT16373A: Features: 16-bit transparent latch 3-State buffers Output capability: +64mA/-32mA TTL input and output switching levels Input and output interface capability to systems at 5V supply Bus-h...

floor Price/Ceiling Price

Part Number:
74LVT16373A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

16-bit transparent latch
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
 



Pinout

  Connection Diagram




Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +4.6 V
IIK DC input diode current VI < 0 50 mA
VI DC input voltage3   0.5 to +7.0 V
IOK DC output diode current VO < 0 50 mA
VOUT DC output voltage3 Output in Off or High state 0.5 to +7.0 V
IOUT DC output current Output in Low state 128 mA
Output in High state 64
Tstg Storage temperature range   65 to +150 °C



Description

The 74LVT16373A is a high-performance BiCMOS product designed for VCC operation at 3.3V.

The 74LVT16373A is a 16-bit transparent D-type latch with non-inverting 3-State bus compatible outputs. The device can be used as two 8-bit latches or one 16-bit latch. When enable (E) input is High, the Q outputs follow the data (D) inputs. When enable is taken Low, the Q outputs are latched at the levels of the D inputs one setup time prior to the High-to-Low transition.


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