74LVQ280

`HIGH SPEED: tPD = 8 ns (TYP.) at VCC = 3.3 V
`COMPATIBLE WITH TTL OUTPUTS
`LOW POWER DISSIPATION: ICC = 2A(MAX.) at TA=25°C
`LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V
`75W TRANSMISSION LINE DRIVING CAPABILITY
`SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
`PCI BUS LEVELS GUARANTEED AT 24 mA
`BALANCED PROPAGATION DELAYS: tPLH @ tPHL
`OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V
`PINAND FUNCTION COMPATIBLE WITH 74 SERIES 280
`IMPROVED LATCH-UP IMMUNITY

The 74LVQ280 is a low voltage CMOS 9 BIT PARITY GENERATOR fabricated with sub-micron  silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.

It is composed of nine data inputs (A to I) and odd/ even parity outputs (ODD and EVEN). The nine data inputs control the output conditions. When the number of high level input is odd, ODD output is kept high and EVEN output low.

Conversely, when the number of high level is even, EVEN output is kept high and ODD low.

The IC generates either odd or even parity making it flexible application. The word-length capability is easily expanded by cascading.

All inputs and outputs of the 74LVQ280 are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.