74LVCH32374A

Features: · 5 V tolerant inputs/outputs for interfacing with 5 V logic· Wide supply voltage range from 1.2 to 3.6 V· CMOS low power consumption· MULTIBYTEä flow-trough standard pin-out architecture· Low inductance multiple power and ground pins for minimum noise and ground bounce· Direct inte...

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SeekIC No. : 004251426 Detail

74LVCH32374A: Features: · 5 V tolerant inputs/outputs for interfacing with 5 V logic· Wide supply voltage range from 1.2 to 3.6 V· CMOS low power consumption· MULTIBYTEä flow-trough standard pin-out architec...

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Part Number:
74LVCH32374A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

· 5 V tolerant inputs/outputs for interfacing with 5 V logic
· Wide supply voltage range from 1.2 to 3.6 V
· CMOS low power consumption
· MULTIBYTEä flow-trough standard pin-out architecture
· Low inductance multiple power and ground pins for minimum noise and ground bounce
· Direct interface with TTL levels
· Bus hold on data inputs
· Typical output ground bounce voltage:
   VOLP < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
· Typical output undershoot voltage:
   VOHV > 2 V at VCC = 3.3 V and Tamb = 25 °C
· Power off disables outputs, permitting live insertion
· Packaged in plastic fine-pitch ball grid array package.



Description

The 74LVCH32374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, the outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 or 5 V environment.

The 74LVCH32374A is a 32-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. The 74LVCH32374A consists of 4 sections of eight edge-triggered flip-flops. A clock (nCP) input and an output enable input (nOE) are provided per 8-bit section.

The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition.

When input nOE is LOW, the contents of the flip-flops are available at the outputs. When input nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops.

The 74LVCH32374A bus hold data input circuits eliminate the need for external pull-up resistors to hold unused inputs.




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