Features: · 5 V tolerant inputs/outputs for interfacing with 5 V logic· Wide supply voltage range of 1.2 to 3.6 V· CMOS low power consumption· MULTIBYTEä flow-trough standard pin-out architecture· Low inductance multiple power and ground pins for minimum noise and ground bounce· Direct interf...
74LVCH32244A: Features: · 5 V tolerant inputs/outputs for interfacing with 5 V logic· Wide supply voltage range of 1.2 to 3.6 V· CMOS low power consumption· MULTIBYTEä flow-trough standard pin-out architectu...
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Symbol |
Parameter |
CONDITIONS |
Min |
Max |
Unit |
VCC |
DC Supply Voltage |
-0.5 |
+6.5 |
V | |
VI |
DC input voltage |
note 1 |
-0.5 |
+6.5 |
V |
IIK |
DC input diode current |
VI < 0 |
-50 |
mA | |
IOK |
DC output diode current |
VO > VCC or VO < 0; note 1 |
±50 |
mA | |
VO |
output voltage |
output HIGH or LOW state; note 1 |
-0.5 |
VCC + 0.5 |
V |
output 3-state; note 1 |
-0.5 |
+6.5 |
V | ||
IO |
DC output source or sink current |
VO = 0 to VCC |
±50 |
mA | |
ICC or IGND |
DC VCC or GND current |
±100 |
mA | ||
Tstg |
Storage temperature |
-65 |
+150 |
||
Ptot |
power dissipation |
temperature range -40 to +85 °C; note 2 |
1000 |
mW |
The 74LVCH32244A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment.
The 74LVCH32244A is a 32-bit non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE.A HIGH on input nOE causes the outputs to assume a high-impedance OFF-state.
To ensure the high-impedance state of the 74LVCH32244A during power-up or power-down, input nOE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
The 74LVCH32244A bus hold data input circuit eliminates the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level (see Fig.3).