74LVCH245APW

Number of Channels per Chip : 8
Output Type : 3-State
Packaging : Tube
Logic Type : CMOS
Maximum Operating Temperature : + 125 C
Supply Voltage - Max : 3.6 V
Supply Voltage - Min : 1.2 V
Package / Case : TSSOP-20
Logic Family : LVC
Output Level : LVTTL
High Level Output Current : - 24 mA
Low Level Output Current : 24 mA
Input Level : LVTTL
Propagation Delay Time : 17 ns


Pinout




Description

The 74LVCH245APW is a type of high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.Inputs is able to be driven from either 3.3V or 5V devices. In 3-State operati on, outputs can deal with 5V. These features accept the use of these devices as translators in a mixed 3.3V/5V env ironment. The 74LVCH245APW is an octal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions.

Features of the 74LVCH245APW are:(1)5-volt tolerant inputs/outputs, for interfacing with 5-volt logic; (2)supply volt age range of 2.7V to 3.6V; (3)complies with JEDEC standard no. 8-1A; (4)CMOS low power consumption; (5)direct int erface with TTL levels; (6)high impedance when VCC = 0V; (7)bushold on all data inputs.

The absolute maximum ratings of the 74LVCH245APW can be summarized as:(1):DC supply voltage is0.5V to +6.5 V;(2):DC input diode current is50 mA when VI is less than 0 ;(3):DC input voltage is0.5V to +6.5 V;(4):DC output diode current is ±50mA when VO is greater than VCC or VO is less than 0 ; (5):DC output voltage: output HIGH or LOW state is0.5V to VCC +0.5;(6):DC output voltage:output 3-State is0.5V to 6.5V;(7):DC output source or sink current is±50mA when VO is 0 to VCC;(8):storage temperature ranges from65°C to +150°C;(9):power dissipatio n per package:plastic mini-pack(above +70°C derate linearly with 8 mW/K) is  500 mW,power dissipation per packa ge:plastic shrink mini-pack(above +60°C derate linearly with 5.5 mW/K) is 500 mW.