Features: •5-volt tolerant inputs/outputs, for interfacing with 5-volt logic•Supply voltage range of 2.7V to 3.6V•Complies with JEDEC standard no. 8-1A•CMOS low power consumption•Direct interface with TTL levels•High impedance when VCC = 0V•Bushold on all ...
74LVCH2373A: Features: •5-volt tolerant inputs/outputs, for interfacing with 5-volt logic•Supply voltage range of 2.7V to 3.6V•Complies with JEDEC standard no. 8-1A•CMOS low power consump...
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•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when VCC = 0V
•Bushold on all data inputs (74LVCH2373A only)
•Integrated 30 damping resistor
SYMBOL | PARAMETER | CONDITIONS | RATING | UNIT |
VCC | DC supply voltage | 0.5 to +6.5 | V | |
IIK | DC input diode current | VI0 | 50 | mA |
VI | DC input voltage | Note 2 | 0.5 to +5.5 | V |
VI/O | DC input voltage range for I/Os | 0.5toVCC+0.5 | V | |
IOK | DC output diode current | VOVCC or VO0 | ±50 | mA |
VOUT | DC output voltage; output HIGH or LOW | Note 2 | 0.5 to VCC +0.5 | V |
VOUT | DC output voltage; output 3-State | Note 2 | 0.5 to +6.5 | V |
IOUT | DC output source or sink current | VO = 0 to VCC | ±50 | mA |
IGND,ICC | DC VCC or GND current | ±100 | mA | |
Tstg | Storage temperature range | 60 to +150 | ||
PTOT |
Power dissipation per package plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP) |
above+70°Cderatelinearlywith8mW/K above +60°C deratelinearlywith5.5mW/K |
500 500 |
mW |
The 74LVC2373A/74LVCH2373A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC2373A/74LVCH2373A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE ) input are common to all internal latches.
When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.