74LVCH16374A

Features:

*5 volt tolerant inputs/outputs for interfacing with 5V logic
*Wide supply voltage range of 1.2 V to 3.6 V
*Complies with JEDEC standard no. 8-1A
*CMOS low power consumption
*MULTIBYTE^TM  flow-through standard pin-out architecture
*Low inductance multiple power and ground pins for minimum
  noise and ground bounce
*Direct interface with TTL levels
*All data inputs have bus hold (74LVCH16374A only)
*High impedance when VCC = 0


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		0.5 to +6.5	V
IIK	DC input diode current	VI<0	±50	mA
VI	DC input voltage	Note 2	0.5 to VCC +0.5	V
IOK	DC output diode current	VO>VCC or VO<0	±50	mA
VO	DC output voltage; output HIGH or LOW state	Note 2	0.5 to V +0.5	V V
	DC output voltage; output 3-State	Note 2	0.5 to 6.5
IO	DC output source or sink current	VO = 0 to VCC	±50	mA
IGND,ICC	DC VCC or GND current		±100	mA
Tstg	Storage temperature range		65 to +150	°C
PTOT	Power dissipation per package plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP)	above +70 derate linearly with 8 mW/K above +60 derate linearly with 5.5 mW/K	500 500	mW

Description

The 74LVCH16374A is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. The 74LVC16374A consists of 2 sections of eight positive edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment.

The flip-flops of the 74LVCH16374A will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition.