74LVCH162374A

Features:

* ESD protection:
   HBM EIA/JESD22-A114-A exceeds 2000 V
   MM EIA/JESD22-A115-A exceeds 200 V
* 5 V tolerant input/output for interfacing with 5 V logic
* Wide supply voltage range of 1.2 to 3.6 V
* Complies with JEDEC standard no. 8-1A
* CMOS low power consumption
* MULTIBYTE(TM) flow-through standard pin-out architecture
* Lowinductancemultiplepowerand groundpinsforminimumnoiseand ground bounce
* Direct interface with TTL levels
* All data inputs have bus hold (74LVCH162374A only)
* High impedance when VCC =0
* Power off disables outputs, permitting live insertion.


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VCC	DC supply voltage		-0.5	+6.5	V
IIK	DC input diode current	VI< 0	-	-50	mA
VI	DC input voltage	Note 1	-0.5	+5.5	V
IOK	DC output diode current	VO>VCC or VO<0	-	±50	mA
VO	DC output voltage       output HIGH or LOW       output 3-state	Note 1 Note 1	-0.5 -0.5	VCC + 0.5 +6.5	V V
IO	DC output diode current	VO = 0 to VCC	-	±50	mA
IGND,ICC	DC VCC or GND current		-	±100	mA
Tstg	storage temperature		-65	+150	°C
PTOT	power dissipation plastic shrink mini-pack (SSOPand TSSOP)	above 60 derate linearly with 5.5 mW/K	-	500	mW

Description

The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. The 74LVC162374A consists of 2 sections of eight edge-triggered flip-flops.A clock (CP) input and an output enable (OE) are provided for each octal.Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment.

The flip-flops of the 74LVCH162374A will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition.