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74LVC821A

Features: • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic• Supply voltage range of 2.7V to 3.6V• Complies with JEDEC standard no. 8-1A• Inputs accept voltages up to 5.5V• CMOS low power consumption• Direct interface with TTL levels• 10-...

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74LVC821A: Features: • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic• Supply voltage range of 2.7V to 3.6V• Complies with JEDEC standard no. 8-1A• Inputs accept volt...

74LVC821A Data Sheet

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Part Number:
74LVC821A
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
• Supply voltage range of 2.7V to 3.6V
• Complies with JEDEC standard no. 8-1A
• Inputs accept voltages up to 5.5V
• CMOS low power consumption
• Direct interface with TTL levels
• 10-bit positive edge-triggered register
• Independent register and 3-State buffer operation
• Flow-through pin-out architecture


Pinout

Connection Diagram


Specifications

Symbol
Parameter
CONDITIONS
RATING
Unit
VCC
DC Supply Voltage
-0.5 to +4.6
V
IIK
DC input diode current
VI <0
50
mA
VI
DC input voltage
Note 2
-0.5 to +4.6
V
VI/O
DC input voltage range for I/Os
0.5 to VCC +0.5
V
IOK
DC output diode current
VO >VCC or VO< 0
±50
mA
VO
DC output voltage;
output HIGH or LOW state
Note 2
-0.5 to VCC + 0.5
V
IO
DC output source or sink current
VO = 0 to VCC
± 50
mA
ICC or IGND
DC VCC or Ground Currentper
± 100
mA
Tstg
Storage temperature range
-65 to +150
PTOT
Power dissipation per package
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
mW
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.


Description

The 74LVC821A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.

The 74LVC821A is a10-bit D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The ten flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the ten flip-flops is available at the outputs.

When OE is HIGH, the outputs of the 74LVC821A go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.




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