Features: `Wide supply voltage range from 1.65 V to 5.5 V`5 V tolerant inputs for interfacing with 5 V logic` Inputs accept voltages up to 5 V` Direct interface with TTL levels` High noise immunity`Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2....
74LVC2G86: Features: `Wide supply voltage range from 1.65 V to 5.5 V`5 V tolerant inputs for interfacing with 5 V logic` Inputs accept voltages up to 5 V` Direct interface with TTL levels` High noise immunity`...
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Symbol |
Parameter |
CONDITIONS |
Min |
Max |
Unit |
VCC |
Supply Voltage |
-0.5 |
+6.5 |
V | |
VI |
input voltage |
[1] |
-0.5 |
+6.5 |
V |
VO |
output voltage |
Active mode[1] |
-0.5 |
VCC + 0.5 |
V |
Power-down mode[1][2] |
-0.5 |
+6.5 |
V | ||
IIK |
input diode current |
VI < 0 |
-50 |
mA | |
IOK |
output diode current |
VO > VCC or VO < 0; note 1 |
±50 |
mA | |
IO |
output source or sink current |
VO = 0 to VCC |
±50 |
mA | |
ICC or IGND |
VCC or GND current |
±100 |
mA | ||
Tstg |
Storage temperature |
-65 |
+150 |
||
Ptot |
power dissipation |
Tamb = -40 °C to +125 °C |
300 |
mW |
The 74LVC2G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this devices as translators in a mixed 3.3 V and 5 V environment.
The 74LVC2G86 is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74LVC2G86 provides the dual 2-input exclusive-OR gate.