74LVC2952A

Features:

• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
• Wide supply voltage range of 1.2 V to 3.6 V
• In accordance with the JEDEC standard no. 8-1 A
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Flow-through pin-out architecture
• 3-State outputs
• Direct interface with TTL levels
• Integrated 30
damping resistor


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		0.5 to +6.5	V
IIK	DC input diode current	VI< 0	50	mA
VI	DC input voltage	Note 2	0.5 to +6.5	V
IOK	DC output diode current	VO >VCC or VO< 0	±50	mA
vI/O	DC output voltage; output HIGH or LOW	Note 2	0.5 to VCC +0.5	V
	DC output voltage; output 3-State	Note 2	0.5 to 6.5
IO	DC output source or sink current	VO = 0 to VCC	±50	mA
IGND, ICC	DC VCC or GND current		±100	mA
Tstg	Storage temperature range		65 to +150	°C
PTOT	Power dissipation per package plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP)	above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K	500 500	mW

Description

The 74LVC2952A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC2952A is an octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional busses. Data applied to the inputs is entered and stored on the rising edge of the clock (CPnn) provided that the clock enable CE nn) is LOW. The data is then present at the 3-State output buffers, but is only accessible when the output enable input (OE nn) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. The 74LVC2952A is identical to the 74LVC2952A but has non-inverting outputs.