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74LVC1G86

Features: ` Wide supply voltage range from 1.65 to 5.5 V` High noise immunity` Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).` ±24 mA output drive (VCC = 3.0 V)` CMOS low power consumption` Latch-up performance exceeds 250 mA` Direct ...

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SeekIC No. : 004251287 Detail

74LVC1G86: Features: ` Wide supply voltage range from 1.65 to 5.5 V` High noise immunity` Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).` ±24 mA ...

74LVC1G86 Data Sheet

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Part Number:
74LVC1G86
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` Wide supply voltage range from 1.65 to 5.5 V
` High noise immunity
` Complies with JEDEC standard:
  JESD8-7 (1.65 to 1.95 V)
  JESD8-5 (2.3 to 2.7 V)
  JESD8B/JESD36 (2.7 to 3.6 V).
` ±24 mA output drive (VCC = 3.0 V)
` CMOS low power consumption
` Latch-up performance exceeds 250 mA
` Direct interface with TTL levels
` Inputs accept voltages up to 5 V
` Multiple package options
` ESD protection:
    HBM EIA/JESD22-A114-A exceeds 2000 V
    MM EIA/JESD22-A115-A exceeds 200 V.
` Specified from -40 to +125 °C.


Pinout

Connection Diagram


Description

The 74LVC1G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 or 5 V devices. These features allow the use of these devices in a mixed 3.3 and 5 V environment.

The 74LVC1G86 is fully specified for partial Power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function.




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