Features: ` Wide supply voltage range from 1.65 to 5.5 V` High noise immunity` Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).` ±24 mA output drive (VCC = 3.0 V)` CMOS low power consumption` Latch-up performance £250 mA` Direct i...
74LVC1G79: Features: ` Wide supply voltage range from 1.65 to 5.5 V` High noise immunity` Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).` ±24 mA ...
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The 74LVC1G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of this device in a mixed 3.3 and 5 V environment.
The 74LVC1G79 is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Information of the 74LVC1G79 on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.