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74LVC1G58

Features: Wide supply voltage range from 1.65 V to 5.5 V5 V tolerant input/output for interfacing with 5 V logicHigh noise immunityComplies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V). 24 mA output drive (VCC = 3.0 V)ESD protection: HBM E...

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SeekIC No. : 004251283 Detail

74LVC1G58: Features: Wide supply voltage range from 1.65 V to 5.5 V5 V tolerant input/output for interfacing with 5 V logicHigh noise immunityComplies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2...

74LVC1G58 Data Sheet

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Part Number:
74LVC1G58
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
   JESD8-7 (1.65 V to 1.95 V)
   JESD8-5 (2.3 V to 2.7 V)
   JESD8B/JESD36 (2.7 V to 3.6 V).
   24 mA output drive (VCC = 3.0 V)
ESD protection:
   HBM EIA/JESD22-A114-B exceeds 2000 V
   MM EIA/JESD22-A115-A exceeds 200 V.
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C.


Pinout

Connection Diagram


Specifications

Symbol Parameter Conditions Min Max Unit
VCC supply voltage   −0.5 +6.5 V
IIK input diode current VI <0 V - −50 mA
VI input voltage   −0.5 +6.5 V
IOK output diode current VO >VCC or VO <0V - ±50 mA
VO output voltage active mode −0.5 +6.5 V
Power-down mode −0.5 +6.5 V
IO output source or sink current VO =0V to VCC - ±50 mA
ICC, IGND VCC or GND current   - ±100 mA
Tstg storage temperature   −65 ±150 °C
Ptot power dissipation Tamb = −40 °C to +125 °C - 300 mW



Description

The 74LVC1G58 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the 74LVC1G58 when it is powered down.

The 74LVC1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.

The three inputs (A, B and C) of the 74LVC1G58 are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

The gate switches at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the hysteresis voltage VH.




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