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74LVC1G18

Features: ` Wide supply voltage range from 1.65 to 5.5 V` 5 V tolerant input/output for interfacing with 5 V logic` High noise immunity` Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V).` ESD protection: HBM EIA/JESD22-A114-A exceeds 20...

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SeekIC No. : 004251273 Detail

74LVC1G18: Features: ` Wide supply voltage range from 1.65 to 5.5 V` 5 V tolerant input/output for interfacing with 5 V logic` High noise immunity` Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD...

74LVC1G18 Data Sheet

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Part Number:
74LVC1G18
Supply Ability:
5000

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Product Details

Description



Features:

` Wide supply voltage range from 1.65 to 5.5 V
` 5 V tolerant input/output for interfacing with 5 V logic
` High noise immunity
` Complies with JEDEC standard:
  JESD8-7 (1.65 to 1.95 V)
  JESD8-5 (2.3 to 2.7 V)
  JESD8B/JESD36 (2.7 to 3.6 V).
` ESD protection:
  HBM EIA/JESD22-A114-A exceeds 2000 V
  MM EIA/JESD22-A115-A exceeds 200 V.
` ±24 mA output drive (VCC = 3.0 V)
` CMOS low power consumption
` Latch-up performance exceeds 250 mA
` Direct interface with TTL levels
` SOT363 and SOT457 package
` Specified from -40 to +85 °C and -40 to +125 °C.


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage   -0.5 +6.5 V
IIK input diode current VI < 0 - -50 mA
VI input voltage  note 1 -0.5 +6.5 V
IOK output diode current  VO > VCC or VO < 0 - ±50 mA
VO output voltage active mode; notes 1 and 2 -0.5 VCC + 0.5 V
Power-down mode; notes 1 and 2 -0.5 +6.5 V
IO output source or sink current VO = 0 to VCC - ±50 mA
ICC, IGND VCC or GND current   - ±100 mA
Tstg storage temperature   -65 +150 °C
Ptot power dissipation Tamb = -40 °C to +125 °C - 300 mW

Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.




Description

The 74LVC1G18 is a high-performance, low-power,low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Input can be driven from either 3.3 or 5 V devices. These features allow the use of these devices in a mixed 3.3 and 5 V environment.

The 74LVC1G18 is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output,preventing the damaging backflow current through the device when it is powered down.

The 74LVC1G18 is a 1-of-2 non-inverting demultiplexer with a 3-state output. The 74LVC1G18 buffers the data on input pin A and passes it either to output 1Y or 2Y,depending on whether the state of the select input (pin S) is LOW or HIGH.




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