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74LVC1G11

Features: Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V). ±24 mA output drive (VCC = 3.0 V) ESD protection: HB...

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SeekIC No. : 004251266 Detail

74LVC1G11: Features: Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3...

74LVC1G11 Data Sheet

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Part Number:
74LVC1G11
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
    JESD8-7 (1.65 V to 1.95 V)
   JESD8-5 (2.3 V to 2.7 V)
   JESD8-B/JESD36 (2.7 V to 3.6 V).
±24 mA output drive (VCC = 3.0 V)
ESD protection:
   HBM EIA/JESD22-A114-B exceeds 2000 V
   MM EIA/JESD22-A115-A exceeds 200 V.
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C.


Pinout

Connection Diagram


Specifications

Symbol Parameter Conditions Min Max Unit
VCC supply voltage   -0.5 +6.5 V
VI input voltage   [1] -0.5 +6.5 V
VO output voltage

active mode

 [1] [2] -0.5 VCC + 0.5 V
Power-down mode [1] [2] -0.5

+6.5

V

IIK input diode current VI < 0 V - -50 mA
IOK output diode current VO > VCC or VO < 0 V - ±50 mA
IO output source or sink current
 VO = 0 V to VCC - ±50 mA
ICC, IGND VCC or GND current   - ±100 mA
Tstg storage temperature   -65 +150
Ptot power dissipation Tamb = -40  to +125 - 250 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.




Description

The 74LVC1G11 is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

The 74LVC1G11 is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output,preventing the damaging backflow current through the device when it is powered down.
 
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times.

The 74LVC1G11 provides a single 3-input AND gate.




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