74LVC1G08

Features:

` Wide supply voltage range from 1.65 V to 5.5 V
` High noise immunity
` Complies with JEDEC standard:
  JESD8-7 (1.65 V to 1.95 V)
  JESD8-5 (2.3 V to 2.7 V)
  JESD8B/JESD36 (2.7 V to 3.6 V).
` ±24 mA output drive (V_CC = 3.0 V)
` CMOS low power consumption
` Latch-up performance £250 mA
` Direct interface with TTL levels
` Inputs accept voltages up to 5 V
` ESD protection:
  HBM EIA/JESD22-A114-B exceeds 2000 V
  MM EIA/JESD22-A115-A exceeds 200 V.
` Multiple package options
` Specified from -40 °C to +85 °C and -40 °C to +125 °C.


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VCC	supply voltage		1.65	5.5	V
VI	input voltage		0	5.5	V
VO	output voltage	active mode	0	VCC	V
		VCC= 0 V; Power-down mode	0	5.5	V
Tamb	operating ambient temperature		-40	+125	°C
tr, tf	input rise and fall times	VCC= 1.65 V to 2.7 V	0	20	ns/V
		VCC= 2.7 V to 5.5 V	0	10	ns/V

Description

The 74LVC1G08 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

The 74LVC1G08 is fully specified for partial power-down applications using I_off. The I_off circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
 
The 74LVC1G08 provides the single 2-input AND function.