Features: •5 volt tolerant inputs/outputs for interfacing with 5V logic
•Wide supply voltage range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•MULTIBYTETM flow-through standard pin-out architecture
•Low inductance multiple power and ground pins for minimum noise and ground bounce
•Direct interface with TTL levels
•All data inputs have bus hold (74LVCH167373A only)
•High impedance when VCC = 0
Specifications
| SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
| VCC |
DC supply voltage |
|
0.5 to +6.5 |
V |
| IIK |
DC input diode current |
VI0 |
50 |
mA |
| VI |
DC input voltage |
Note 2 |
0.5 to +5.5 |
V |
| IOK |
DC output diode current |
VOVCC or VO0 |
±50 |
mA |
| VO |
DC output voltage; output HIGH or LOW |
Note 2 |
0.5 to VCC +0.5 |
V |
| DC output voltage; output 3-State |
Note 2 |
0.5 to +6.5 |
| IOUT |
DC output source or sink current |
VO = 0 to VCC |
±50 |
mA |
| IGND,ICC |
DC VCC or GND current |
|
±100 |
mA |
| Tstg |
Storage temperature range |
|
60 to +150 |
|
| PTOT |
Power dissipation per package
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP) |
above+70°Cderatelinearlywith8mW/K
above +60°C deratelinearlywith5.5mW/K |
500
500 |
mW |
DescriptionThe 74LVC16373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. One latch enable (LE) input and one output enable (OE ) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment.
The 74LVC16373A consists of 2 sections of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information of the 74LVC16373A that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74LVC16373A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs.
74LVC16373A Data Sheet
