74LVC163

The 74LVC163 is a high-performance, low-power, low-voltage,Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

The 74LVC163 is a synchronous presettable binary counter which features an internal lookhead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP).The outputs (Q₀ to Q₃) of the counters of the 74LVC163 may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D₀ to D₃) to be loaded into the counter on the positivegoing edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q₀ to Q₃) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for PE are met).

This action occurs regardless of the levels at CP, PE, CET and CEP inputs This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate.

The lookahead carry simplifies serial cascading of the counters.Both count enable inputs (CEP and CET) must be HIGH to count.The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q₀. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP setup time, according to the following formula:

fmax =         _____________________1__________
                               tp_(max) (CP to TC) + t_SU (CEP to CP)