74LVC125APW

The 74LVC125APW is one member of the 74LVC125A family which is designed as the high performance, low-power, low-voltage Si-gate CMOS device that consists of four non-inverting buffers/line drivers with 3-state outputs.

Features of the 74LVC125APW are:(1)5-volt tolerant inputs/outputs, for interfacing with 5-volt logic; (2)Supply voltage range of 1.2 V to 3.6 V; (3)Complies with JEDEC standard no. 8-1A; (4)CMOS low power consumption; (5)Direct interface with TTL levels; (6)High impedance when Vcc = 0 V.

The absolute maximum ratings of the 74LVC125APW can be summarized as:(1)DC supply voltage: -0.5 to +6.5 V;(2)DC input diode current: -50 mA;(3)DC input voltage: -0.5 to +6.5 V;(4)DC output diode current: +/-50 mA;(5)DC output voltage; output HIGH or LOW state: -0.5 to VCC +0.5 V;(6)DC output voltage; output 3-State: -0.5 to 6.5 V;(7)DC output source or sink current: +/-50 mA;(8)DC VCC or GND current: +/-100 mA;(9)Storage temperature range: -65 to +150 °C;(10)Power dissipation per package - plastic mini-pack (SO): 500 mW.

The electrical characteristics of the 74LVC125APW can be summarized as:(1)Additional quiescent supply current per input pin: 5 to 500 uA;(2)Quiescent supply current: 0.1 to 10 uA;(3)Power off leakage supply: 0.1 to +/-10 uA;(4)3-State output OFF-state current: 0.1 to +/-5 uA;(5)Input leakage current: +/-0.1 to +/-5 uA. If you want to know more information about the 74LVC125APW, please download the datasheet in www.seekic.com or www.chinaicmart.com .