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74LVC125

Features: • Wide supply voltage range of 1.2 to 3.6 V• In accordance with JEDEC standard no. 8-1A• Inputs accept voltages up to 5.5 V• CMOS lower power consumption• Direct interface with TTL levels• Output drive capability 50  transmission lines at 85°CPinoutSp...

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74LVC125: Features: • Wide supply voltage range of 1.2 to 3.6 V• In accordance with JEDEC standard no. 8-1A• Inputs accept voltages up to 5.5 V• CMOS lower power consumption• Dir...

74LVC125 Data Sheet

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Part Number:
74LVC125
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• Wide supply voltage range of 1.2 to 3.6 V
• In accordance with JEDEC standard no. 8-1A
• Inputs accept voltages up to 5.5 V
• CMOS lower power consumption
• Direct interface with TTL levels
• Output drive capability 50  transmission lines at 85°C


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +6.5 V
IIK DC input diode current VI< 0 50 mA
VI DC input voltage Note 2 0.5 to +5.5 V
VI/O DC input voltage range for I/Os   0.5 to VCC +0.5 V
IOK DC output diode current VO>VCC or VO < 0 ±50 mA
VOUT DC output voltage Note 2 0.5 to VCC +0.5 V
IOUT DC output source or sink current VO = 0 to VCC ±50 mA
IGND,ICC DC VCC or GND current   ±100 mA
Tstg Storage temperature range   60 to +150 °C
PTOT Power dissipation per package
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)		 above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K		 500
500		 mW

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.




Description

The 74LVC125 is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

The 74LVC125 consists of four non-inverting buffers/line drivers with 3-State outputs. The 3-State outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high impedance OFF-state.




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