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74LV74

Features: • Wide operating voltage: 1.0 to 5.5V• Optimized for Low Voltage applications: 1.0 to 3.6V• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V• Typical VOLP (output ground bounce)  0.8V @ VCC = 3.3V,Tamb = 25°C• Typical VOHV (output VOH undershoot) ...

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SeekIC No. : 004251189 Detail

74LV74: Features: • Wide operating voltage: 1.0 to 5.5V• Optimized for Low Voltage applications: 1.0 to 3.6V• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V• Typical VOLP...

74LV74 Data Sheet

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Part Number:
74LV74
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Wide operating voltage: 1.0 to 5.5V
• Optimized for Low Voltage applications: 1.0 to 3.6V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Typical VOLP (output ground bounce)  0.8V @ VCC = 3.3V,Tamb = 25°C
• Typical VOHV (output VOH undershoot)  2V @ VCC = 3.3V,Tamb = 25°C
• Output capability: standard
• ICC category: flip-flops


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +7.0 V
±IIK DC input diode current VI < 0.5 or VI > VCC + 0.5V 20 mA
±IOK DC output diode current VO < 0.5 or VO > VCC + 0.5V 50 mA
±IO DC output source or sink current
standard output
s 0.5V < VO < VCC + 0.5V 		25 mA
±IGND,
±ICC
DC VCC or GND current for types with standard outputs 		  50 mA
Tstg Storage temperature range   65 to +150 °C
Ptot Power dissipation per package
plastic DIL
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)		 for temperature range: 40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K

750
500
400
 mW



Description

The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74.

The 74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)inputs; also complementary Q and Q outputs.

The set and reset of the 74LV74 are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt-trigger action of the 74LV74 in the clock input makes the circuit highly tolerant to slower clock rise and fall times.




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