Features: • Optimized for Low Voltage applications: 1.0V to 3.6V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, Tamb = 25°C
• Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, Tamb = 25°C
• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-State outputs
• Shift register with direct clear
• Output capability:
parallel outputs; bus driver
serial output; standard
• ICC category: MSIApplication• Serial-to-parallel data conversion
• Remote control holding registerPinout
Specifications
| SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
| VCC |
DC supply voltage |
|
0.5 to +4.6 |
V |
| ±IIK |
DC input diode current |
VI < 0.5 or VI > VCC + 0.5V |
20 |
mA |
| ±IOK |
DC output diode current |
VO < 0.5 or VO > VCC + 0.5V |
50 |
V |
| ±IO |
DC output source or sink current
standard outputs
bus driver outputs |
0.5V < VO < VCC + 0.5V |
25
35 |
mA |
±IGND,
±ICC |
DC VCC or GND current for types with
standard outputs
bus driver outputs |
|
50
70 |
mA |
| Tstg |
storage temperature |
|
65 to +150 |
°C |
| PTOT |
Power dissipation per package
plastic DIL
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP) |
for temperature range: 40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K |
750
500
400 |
°C |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DescriptionThe 74LV595 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT595.
The74LV595 is an 8-stage serial shift register with a storage register and 3-State outputs. The shift register and storage register have separate clocks.
Data is shifted on the positive-going transitions of the SHCP input.
The data of the 74LV595 in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
The shift register of the 74LV595 has a serial input (DS) and a serial standard output (Q7') all for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-State bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
74LV595 Data Sheet
