Features: • Optimized for Low Voltage applications: 1.0 to 5.5V• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V• Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,Tamb = 25°C• Typical VOHV (output VOH undershoot) > 2V @ VCC = 3.3V,Tamb = 25°C• DC trig...
74LV423: Features: • Optimized for Low Voltage applications: 1.0 to 5.5V• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V• Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,...
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SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
VCC |
DC supply voltage |
0.5 to +7.0 |
V | |
±IIK |
DC input diode current |
VI<0.5 or VI>VCC + 0.5V |
20 |
mA |
±IOK |
DC output diode current |
VO<0.5 or VO>VCC + 0.5V |
50 |
mA |
±IO |
DC output source or sink current standard outputs bus driver outputs |
0.5V<VO<VCC + 0.5V |
25 35 |
mA |
±IGND,±ICC |
DC VCC or GND current for types with standard outputs bus driver outputs |
50 70 |
mA | |
Tstg |
Storage temperature range |
65 to +150 |
°C | |
PTOT |
Power dissipation per package plastic DIL plastic mini-pack (SO) plastic shrink mini-pack(SSOP and TSSOP) |
for temperature range: 40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K |
750 500 400 |
mW |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The 74LV423 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT423.
The 74LV423 is a dual retriggerable monostable multivibrator with output pulse width control by three methods. The basic pulse time is programmed by selection of an external resistor (REXT) and capacitor (CEXT). They are normally connected as shown in Figure 1. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. Alternatively, an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering. Figures 2 and 3 illustrate pulse control by retriggering and early reset. The basic output pulse width of the 74LV423 is essentially determined by the values of the external timing components REXT and CEXT. For pulse width when CEXT <10000pF,see Figure 6. When CEXT > 10,000pF, the typical output pulse width is defined as: tW = 0.45 * REXT * CEXT (typ.), where tW = pulse width in ns; REXT = external resistor in KW; and CEXT = external capacitor in pF. Schmitt-trigger action in the nA and nB inputs makes the circuit highly tolerant of slower input rise and fall times.