74LV377N

Output Type :
Low Level Output Current :
Number of Circuits : 1
Supply Voltage - Max : 3.6 V
Maximum Operating Temperature : + 125 C
Polarity : Non-Inverting
Input Type : Single-Ended
Mounting Style : Through Hole
Packaging : Tube
Package / Case : DIP-20
Logic Type : D-Type Edge Triggered Flip-Flop
High Level Output Current : - 6 mA
Logic Family : LV
Propagation Delay Time : 13 ns at 3.3 V


Description

The 74LV377N belongs to the 74LV377 family which has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. The 74LV377 is a low±voltage CMOS device and is pin and function compatible with 74HC/HCT377.

The features of 74LV377N can be summarized as (1)optimized for low voltage applications: 1.0 to 3.6V; (2)accepts TTL input levels between VCC = 2.7V and VCC = 3.6V; (3)typical VOLP (output ground bounce) <0.8V @ VCC = 3.3V, Tamb = 25°C; (4)typical VOHV (output VOH undershoot) <2V @ VCC = 3.3V, Tamb = 25°C; (5)ideal for addressable register applications; (6)data enable for address and data synchronization applications; (7)Eight positive-edge triggered D-type flip-flops; (8)output capability: standard; (9)ICC category: MSI.

The absolute maximum ratings of 74LV377N are (1)VCC DC supply voltage: -0.5 to +4.6 V; (2)±IIK DC input diode current(VI < -0.5 or VI > VCC + 0.5V): 20mA; (3)±IOK DC output diode current(VO < -0.5 or VO > VCC + 0.5V): 50mA; (4)±IO DC output source or sink current -bus driver outputs(-0.5V < VO < VCC + 0.5V): 25mA; (5)±IGND, ±ICC DC VCC or GND current for types with bus driver outputs: 50mA; (6)Tstg storage temperature range: -65 to +150 °C; (7)power dissipation per package for temperature range: -40 to +125°C-plastic DIL(above +70°C derate linearly with 12mW/K)/-plastic mini-pack (SO)(above +70°C derate linearly with 8 mW/K)/-plastic shrink mini-pack (SSOP and TSSOP)(above +60°C derate linearly with 5.5 mW/K): 750/500/400mW.(1. Stresses beyond those listed may cause permanent damage to the 74LV377N. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings of the 74LV377N are observed.)