74LV377

Features:

• Optimized for Low Voltage applications: 1.0 to 3.6V
• Accepts TTL input levels between V_CC = 2.7V and V_CC = 3.6V
• Typical V_OLP (output ground bounce)  0.8V @ V_CC = 3.3V, T_amb = 25°C
• Typical V_OHV (output VOH undershoot)  2V @ V_CC = 3.3V, T_amb = 25°C
• Ideal for addressable register applications
• Data enable for address and data synchronization applications
• Eight positive-edge triggered D-type flip-flops
• Output capability: standard
• I_CC category: MSI


Pinout




Specifications

In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		0.5 to +7.0	V
±IIK	DC input diode current	VI < 0.5 or VI > VCC + 0.5V	20	mA
±IOK	DC output diode current	VO < 0.5 or VO > VCC + 0.5V	50	mA
±IO	DC output source or sink current standard outputs	0.5V < VO < VCC + 0.5V	25	mA
±IGND, ±ICC	DC VCC or GND current for types with standard outputs		50	mA
Tstg	Storage temperature range		65 to +150	°C
PTOT	Power dissipation per package plastic DIL plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP)	for temperature range: 40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K	750 500 400	mW

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

Description

The 74LV377 is a lowvoltage CMOS device and is pin and function compatible with 74HC/HCT377.

The 74LV377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Q_n) of the flip-flop. The E input of the 74LV377 must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation.