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74LV373

Features: • Wide operating voltage: 1.0 to 5.5V• Optimized for Low Voltage applications: 1.0V to 3.6V• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V• Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, Tamb = 25°C• Typical VOHV (output VOH unders...

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SeekIC No. : 004251169 Detail

74LV373: Features: • Wide operating voltage: 1.0 to 5.5V• Optimized for Low Voltage applications: 1.0V to 3.6V• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V• Typical VOL...

74LV373 Data Sheet

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Part Number:
74LV373
Supply Ability:
5000

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Product Details

Description



Features:

• Wide operating voltage: 1.0 to 5.5V
• Optimized for Low Voltage applications: 1.0V to 3.6V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, Tamb = 25°C
• Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, Tamb = 25°C
• Common 3-State output enable input
• Output capability: bus driver
• ICC category: MSI


Pinout

Connection Diagram


Specifications

In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +7.0 V
±IIK DC input diode current VI < 0.5 or VI > VCC + 0.5V 20 mA
±IOK DC output diode current VO < 0.5 or VO > VCC + 0.5V 50 mA
±IO DC output source or sink current
standard outputs		 0.5V < VO < VCC + 0.5V 35 mA
±IGND,
±ICC		 DC VCC or GND current for types with
standard outputs		   70 mA
Tstg Storage temperature range   65 to +150 °C
PTOT Power dissipation per package
plastic DIL
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)		 for temperature range: 40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K		 750
500
400		 mW



Description

The 74LV373 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT373.

The 74LV373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches.

The '373' consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes.

When LE of the 74LV373 is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

The '373' is functionally identical to the '573', but the '573' has a different pin arrangement.




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