Features: • Optimized for low voltage applications: 1.0 to 3.6 V• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 2...
74LV257: Features: • Optimized for low voltage applications: 1.0 to 3.6 V• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V• Typical VOLP (output ground bounce) < 0.8 V at VC...
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SYMBOL | PARAMETER | CONDITIONS | RATING | UNIT |
VCC | DC supply voltage | 0.5 to +4.6 | V | |
±IIK | DC input diode current | VI < 0.5 or VI > VCC + 0.5V | 20 | mA |
±IOK | DC output diode current | VO < 0.5 or VO > VCC + 0.5V | 50 | mA |
±IO | DC output source or sink current bus driver outputs |
0.5V < VO < VCC + 0.5V | 35 | mA |
±IGND, ±ICC |
DC VCC or GND current for types with bus driver outputs |
70 | mA | |
Tstg | Storage temperature range | 65 to +150 | °C | |
PTOT | Power dissipation per package plastic DIL plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP) |
for temperature range: 40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K |
750 500 400 |
mW |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The 74LV257 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT257.
The 74LV257 is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1l0 to 4l0) are selected when input S is LOW and the data inputs from source 1 (1l1 to 4l1) are selected when S in HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) from the selected inputs. The 74LV257 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance OFF-state when OE is HIGH.
The logic equations for the outputs are:
1Y = OE × (1l1 × S + 1l0 × S)
2Y = OE × (2l1 × S + 2l0 × S)
3Y = OE × (3l1 × S + 3l0 ×S)
4Y = OE × (4l1 × S + 4l0 × S)