74LV175

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

The 74LV175 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT175.

The 74LV175 has four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register of the 74LV175 is fully edge-triggered. The state of each D input, one set-up time prior to the LOW-to-HIGH clock transition, is transferred to the corresponding output (Q_n) of the flip-flop.

All Q_n outputs of the 74LV175 will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input.

The 74LV175 is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements.