74LV174

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

The 74LV174 is a lowvoltage Sigate CMOS device and is pin and function compatible with the 74HC/HCT174.

The 74LV174 has six edgetriggered Dtype flipflops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flipflops simultaneously.

The register of the 74LV174 is fully edgetriggered. The state of each D input, one setup time prior to the LOWtoHIGH clock transition, is transferred to the corresponding output of the flipflop.

A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs.

The 74LV174 is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements.