74LV165N

Counter Shift Registers PRLLEL-LOAD 8BIT S/R

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SeekIC No. : 00420375 Detail

74LV165N: Counter Shift Registers PRLLEL-LOAD 8BIT S/R

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US $ .22~.32 / Piece | Get Latest Price
Part Number:
74LV165N
Mfg:
NXP Semiconductors
Supply Ability:
5000

Price Break

  • Qty
  • 0~1
  • 1~25
  • 25~100
  • 100~250
  • Unit Price
  • $.32
  • $.28
  • $.24
  • $.22
  • Processing time
  • 15 Days
  • 15 Days
  • 15 Days
  • 15 Days
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Upload time: 2024/11/23

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Product Details

Quick Details

Counting Sequence : Parallel to Serial Number of Circuits : 1
Package / Case : SOT-38 Logic Family : LV
Logic Type : CMOS Number of Input Lines : 9
Propagation Delay Time : 18 ns Maximum Operating Temperature : + 125 C
Minimum Operating Temperature : - 40 C Packaging : Tube    

Description

Counter Type :
Output Type :
Minimum Operating Temperature : - 40 C
Number of Circuits : 1
Maximum Operating Temperature : + 125 C
Logic Type : CMOS
Number of Input Lines : 9
Packaging : Tube
Logic Family : LV
Package / Case : SOT-38
Counting Sequence : Parallel to Serial
Propagation Delay Time : 18 ns


Description

The 74LV165N belongs to 74LV165 family which is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT165. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0Q1Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The 74LV165N is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.

The features of the 74LV165N can be summarized as (1)wide operating voltage: 1.0 to 5.5 V; (2)optimized for low voltage applications: 1.0 to 3.6 V; (3)accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V; (4)typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C; (5)typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C; (6)asynchronous 8-bit parallel load; (7)synchronous serial input; (8)output capability: standard; (9)ICC category: MSI.

The absolute maximum ratings of the 74LV165N are (1)VCC DC supply voltage: -0.5 to +7.0 V; (2)±IIK DC input diode current(VI < -0.5 or VI > VCC + 0.5V): 20 mA; (3)±IOK DC output diode current(VO < -0.5 or VO > VCC + 0.5V): 50 mA; (4)±IO DC output source or sink current- standard outputs(-0.5V < VO < VCC + 0.5V): 25 mA; (5)±IGND, ±ICC DC VCC or GND current for types with-standard outputs: 50 mA; (6)Tstg storage temperature range of the 74LV165N: -65 to +150 °C; (7)Ptot power dissipation per package for temperature range: -40 to +125°C,plastic DIL above +70°C derate linearly with 12mW/K/plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K/plastic shrink mini-pack (SSOP and TSSOP)above +60°C derate linearly with 5.5 mW/K: 750/500/400mW.(1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the 74LV165N at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.).




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