74LV165A

The 74LV165A is a high-performance, low-power,low-voltage, Is-gate CMOS device and superior to mostadvanced CMOS compatible TTL families.Schmitt-trigger action at all inputs makes the circuittolerant for slower input rise and fall times.
This device is fully specified for partial-power-downapplications using Ioff. The Ioff circuitry disables the output, preventing the damaging current back flow through thedevice when it is powered down.
The 74LV165A is an 8-bit parallel-load or serial-in shiftregister with complementary serial outputs (Q7 and Q7available from the last stage. When the parallel-load input(PL) is LOW, parallel data from the inputs D0 to D7 areloaded into the register asynchronously. When input PL isHIGH, data enters the register serially at the input DS andshifts one place to the right (Q0®Q1®Q2, etc.) with eachpositive-going clock transition. This feature allowsparallel-to-serial converter expansion by tying the outputQ7 to the input DS of the succeeding stage.
The clock input of the 74LV165A is a gate-OR structure which allows oneinput to be used as an active LOW clock enable input (CE)
input. The pin assignment of the 74LV165A for the inputs CP and CE isarbitrary and can be reversed for layout convenience. TheLOW-to-HIGH transition of the input CE should only takeplace while CP HIGH for predictable operation.