74LV107

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed

The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107.

The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.

The reset (nR) of the 74LV107 is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.

Schmitt-trigger action of the 74LV107 in the clock input makes the circuit highly tolerant to slower clock rise and fall times.