74HC/HCT162

Features:

· Synchronous counting and loading
· Two count enable inputs for n-bit cascading
· Positive-edge triggered clock
· Synchronous reset
· Output capability: standard
· I_CC category: MSI

Pinout




Description

   The 74HC/HCT162 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

   The 74HC/HCT162 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting.

   Synchronous operation of the 74HC/HCT162 is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP).

   The outputs (Q₀ to Q₃) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D₀ to D₃) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable
inputs (CEP and CET).

   For the "162" the clear function is synchronous.

   A LOW level  of the 74HC/HCT162 at the master reset input (MR) sets all four outputs of the flip-flops (Q₀ to Q₃) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for MRare met). This action occurs regardless of the levels at PE, CET and CEP inputs.

   This synchronous reset feature of the 74HC/HCT162 enables the designer to modify the maximum count with only one external NAND gate.

   The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q₀. This pulse can be used to enable the next cascaded stage.

   The maximum clock frequency of the 74HC/HCT162 for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:
                                     1
fmax =   -----------------------------------------------------
             t_{P max} ( ) CP to TC ( ) t_SU (CEP to CP) +