Features: · Non-inverting data path· Output capability: standard· ICC category: MSIPinoutDescription The 74HC/HCT157 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT157 are quad...
74HC/HCT157: Features: · Non-inverting data path· Output capability: standard· ICC category: MSIPinoutDescription The 74HC/HCT157 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottk...
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Features: · Output capability: standard· ICC category: SSIPinoutDescription The 74HC/HCT02 are hig...
Features: · Level shift capability· Output capability: standard (open drain)· ICC category: SSIPin...
The 74HC/HCT157 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT157 are quad 2-input multiplexers which select 4 bits of data from two sources under the control of a common data select input (S). The four outputs present the selected data in the true (non-inverted) form. The enable input (E ) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions.
Moving the data from two groups of registers of the 74HC/HCT157 to four common output buses is a common use of the "157". The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator.
The 74HC/HCT157 is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common.
The "157" is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S.
The logic equations are:
1Y = E .(1l1.S + 1l0.S )
2Y = E .(2l1.S + 2l0.S )
3Y = E .(3l1.S + 3l0.S )
4Y = E .(4l1.S + 4l0.S )
The "157" is identical to the "158" but has non-inverting (true) outputs.