74HC/HCT112

Features:

· Asynchronous set and reset
· Output capability: standard
· I_CC category: flip-flops



Pinout




Description

   The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

   The 74HC/HCT112 are dual negative-edge triggered JK-type flip-flops featuring individual nJ, nK, clock (nCPP),set (nS_D) and reset (nR_D) inputs.

   The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless of the levels at the other inputs.

   A HIGH level of the 74HC/HCT112 at the clock (nCP) input enables the nJ and nK inputs and data will be accepted. The nJ and nK inputs control the state changes of the flip-flops as shown in the function table. The nJ and nK inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Output state changes are initiated by the HIGH-to-LOW transition of nCP.

   Schmitt-trigger action of the 74HC/HCT112 in the clock input makes the circuit highly tolerant to slower clock rise and fall times.